The present invention relates generally to a structure and method of forming integrated circuits (ICs) having multiple layers of metal interconnects. More particularly, the present invention relates to a method of forming a metal-insulator-metal (MIM) capacitor for such ICs which requires no additional mask operations during formation, and wherein the capacitor has a relatively large value of capacitance relative to the planar surface area it consumes, and linear signal response characteristics.
In semiconductor manufacturing, capacitors are commonly employed in digital and memory ICs for a variety of purposes. Such purposes include storing electrical charge, blocking DC voltage levels, and stabilizing power supplies. Typical capacitors used in semiconductor devices may have the structure of a metal oxide semiconductor (MOS) type, P-N junction type, polysilicon-insulator-polysilicon (PIP) type, metal-insulator-metal (MIM) type, etc. The type of capacitor utilized in the semiconductor device typically depends on the application and desired response characteristics of the IC.
In memory ICs, for example, dynamic random access memories (DRAMs), a capacitor is used to hold enough charge to represent a detectable logic state. Polysilicon is typically used to construct the plates of the capacitor, thus forming a PIP capacitor. Polysilicon is not necessarily the optimum material to form the capacitor plates because its doping characteristics result in variable capacitance in the polysilicon plate-polysilicon plate capacitor. In polysilicon capacitors, the value of capacitance varies relative to the voltage level applied to the capacitor. The resistance of the polysilicon tends to be dependent on, and therefore a function of, the level of voltage applied to the polysilicon. Polysilicon capacitors are also frequently located in positions in the IC where the surrounding IC components degrade the performance of the capacitor. For example, locating the capacitor on the substrate increases the parasitic effect on the capacitor, further degrading its performance.
Despite these effects, the variance in capacitance is not of primary concern in memory ICs because the capacitor is required to accept charge, to hold some or all of the charge for a period of time, and then discharge; all in a reliable manner. Furthermore, since polysilicon is also used to fabricate other components of the IC, such as transistors and conductors, the plates of the capacitors can be formed simultaneously with the other components of the IC, thus simplifying the construction process and reducing fabrication costs.
In analog circuit applications, on the other hand, capacitors are frequently used as impedance elements whose response characteristic must be generally linear. If the impedance of the capacitor is not fixed and reliably ascertainable, the response of the capacitor will vary non-linearly. As a result, the performance of the analog circuit may be unsatisfactory.
The development of system level integrated circuits (SLICs) and application specific integrated circuits (ASICs) have combined linear or analog circuitry and digital circuitry on the same IC. In such applications, linear capacitors have become somewhat problematic. Polysilicon is not a desirable material from which to form linear capacitors because of its non-linear response characteristics. The fabrication technology for memory capacitors is not generally applicable for fabricating capacitors that may be required to serve as both digital components and analog components.
Capacitors also affect the cost of the IC. In general, the cost of the IC is directly related to the size or surface area of the substrate upon which the IC is constructed. If the IC components require a large amount of space, a larger substrate is required, and the IC cost increases.
The ongoing evolution of miniaturizing ICs has resulted in reduced costs and more circuit functionality for a given substrate size and manufacturing cost. For example, only a few years ago, spacing between adjoining circuit elements in a typical IC was in the neighborhood of two to three microns. Today, many ICs are being designed at spacing distances as small as 0.35 microns or less. To accommodate narrower spacing, the electrical conductors are reduced in width. Metal conductors have also been substituted for polysilicon conductors because the metal conductors provide better signal conducting capabilities. The substitution of metal conductors for polysilicon conductors consequently forms a MIM structure capacitor.
Decreasing the size of devices such as, for example, a MIM capacitor is possible, in part, as a result of advanced planarization techniques such as chemical mechanical polishing (CMP). CMP smooths relatively significant variations in the height of the different components to a planar surface. Smoothing the variable-height topography to a planar surface allows typical lithographic semiconductor fabrication techniques to be used to form considerably more layers than were previously possible in IC construction. Previously, only one or two layers were typically constructed before the topography variations created such significant depth of focus problems with lithographic processes that any further precision fabrication of layered elements was prevented. However, with the introduction of CMP, the number of layers of the IC is no longer limited by the topography. Some present ICs are formed by as many as five or more separate metal or interconnect layers, each of which is separated by a CMP planarized dielectric layer. Consequently, CMP has created the opportunity to incorporate more circuitry on a single substrate in a single IC.
The process of manufacturing thin film MIM capacitors typically uses a multilayer-wiring process incorporating CMP to achieve high integration levels in the IC. More specifically, the customary method of manufacturing MIM capacitors requires an additional lithographic mask level in the production process along with CMP in order define the capacitor region and to isolate the capacitor from other components due to the structure of the capacitor. The structure of a high-capacitance MIM capacitor typically comprises one or more trenches, whereby electrodes of the capacitor follow the topography of the trenches, thus increasing the relative surface area of the electrodes, and thereby increasing the capacitance of the capacitor. Increasing the relative surface area of the capacitor electrodes while maintaining a relatively small footprint of the capacitor on the substrate is essential to attaining smaller and smaller ICs. The addition of a mask level in the customary IC production process adds both cost and time to the manufacturing process. Consequently, a need exists in the industry for a method of manufacturing a MIM capacitor without requiring an additional mask step.
The following presents a simplified summary of the invention in order to provide a basic understanding of some aspects of the invention. This summary is not an extensive overview of the invention. It is intended to neither identify key or critical elements of the invention nor delineate the scope of the invention. Its purpose is to present some concepts of the invention in a simplified form as a prelude to the more detailed description that is presented later.
The present invention relates generally to a structure and method of fabrication of an IC capacitor with a MIM structure without requiring an additional lithographic mask operation.
Customary methods of manufacturing MIM capacitors require an additional mask operation in the IC production process flow to define a capacitor region and to separate it from pure interconnect structures. The present invention is directed to a method of manufacturing a MIM capacitor utilizing standard IC production processes without an additional lithographic mask operation by forming enlarged vias and standard vias during a step where only standard vias are ordinarily formed, and by utilizing advanced planarization techniques such as chemical mechanical polishing (CMP), thereby defining isolated capacitor regions. Elimination of additional masking operations allows for more economical and efficient manufacturing of capacitors.
Additionally, the present invention is directed to a structure and method of manufacturing high-capacitance MIM capacitors wherein MIM capacitor electrode surface areas are large relative to the surface area of the substrate upon which the capacitor is constructed. In one exemplary aspect of the present invention, capacitor electrode surface area is increased by forming one or more enlarged deep vias, wherein the enlarged deep vias are formed over a previously-formed conductive layer without an additional mask operation. In another exemplary aspect of the present invention, capacitor electrode surface area is increased by using a previously-patterned conductive layer as a mask for forming one or more enlarged deep vias without an additional mask operation. Another exemplary aspect of the present invention is a method of forming a capacitor structure with a very large capacitor electrode surface area and a means to electrically connect the capacitor to other components without an additional mask operation. Yet another exemplary aspect of the present invention is a method of forming a stacked capacitor with large capacitor electrode surface areas without an additional mask operation.
To the accomplishment of the foregoing and related ends, the invention comprises the features hereinafter filly described and particularly pointed out in the claims. The following description and the annexed drawings set forth in detail certain illustrative embodiments of the invention. These embodiments are indicative, however, of but a few of the various ways in which the principles of the invention may be employed. Other objects, advantages and novel features of the invention will become apparent from the following detailed description of the invention when considered in conjunction with the drawings.